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A 10-bit 5-MS/s successive approximation ADC cell used in a 70-MS/s ADC array in 1.2-μm CMOS

Authors :
Jiren Yuan
Christer Svensson
Source :
IEEE Journal of Solid-State Circuits. 29:866-872
Publication Year :
1994
Publisher :
Institute of Electrical and Electronics Engineers (IEEE), 1994.

Abstract

A 10-bit 5-MS/s successive approximation ADC cell and a 70-MS/s parallel ADC array based on this cell, designed and fabricated in a 1.2-/spl mu/m CMOS process, are presented. The ADC cell was designed to have an input bandwidth of more than 35 MHz and a sampling time of 14 nS at a clock rate of 70 MHz. The parallel ADC array consists of 14 such cells which are timed in one clock cycle skew successively in order to obtain digitized data every clock cycle. A two-step principle based on unsymmetrical dual-capacitor charge-redistribution-coupling has been used. With the help of a reset function, the comparator presents a fast response to the successive comparison. Each successive approximation ADC cell occupies an area of 0.6 mm/sup 2/ and the core of the parallel ADC array occupies an area of 2.7/spl times/3.3 mm/sup 2/. The power consumptions for the cell and the parallel ADC array are 18 mW and 267 mW respectively. >

Details

ISSN :
00189200
Volume :
29
Database :
OpenAIRE
Journal :
IEEE Journal of Solid-State Circuits
Accession number :
edsair.doi...........c75a9a305db50f7a9a124b0407999e0d
Full Text :
https://doi.org/10.1109/4.297689