A dB-linear switched-resistor CMOS programmable gain amplifier with DC offset cancellation

A programmable gain amplifier (PGA) with DC offset cancellation (DCOC) is designed by 0.18 μm CMOS process in this paper. The PGA adopts two-stage in cascade based on a novel feedback structure, which realizes a constant 3-dB gain step and avoids using multiplexing decoder. The proposed DCOC function block features an adequately low cut-off frequency and completes the challenge of integration on chip. Post-simulation results show that the PGA has a variable gain range of 0–45 dB, and 99.7% of the input-referred DC offset residue is less than 0.383 mV, with a standard deviation of 0.112 mV, reduced by 97.68%.