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Impedance design for multi-layered vias

Authors :
Xiaoxiong Gu
Mark B. Ritter
Albert E. Ruehli
Source :
2008 IEEE-EPEP Electrical Performance of Electronic Packaging.
Publication Year :
2008
Publisher :
IEEE, 2008.

Abstract

This paper presents a methodology based on a semi-analytical scattering model to pre-design the characteristic impedance of multi-layered through hole vias by choosing appropriate via geometrical parameters, dielectric property, and the placement of ground vias. A linear model as a function of design parameters above is further applied to analyze the statistical variation of impedance for different tolerance specification.

Details

Database :
OpenAIRE
Journal :
2008 IEEE-EPEP Electrical Performance of Electronic Packaging
Accession number :
edsair.doi...........c8bee3f78bd24018ad0850ce1204d9e6
Full Text :
https://doi.org/10.1109/epep.2008.4675944