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Analysis and design of class-O RF power amplifiers for wireless communication systems
- Source :
- Analog Integrated Circuits and Signal Processing. 89:317-325
- Publication Year :
- 2016
- Publisher :
- Springer Science and Business Media LLC, 2016.
-
Abstract
- In this paper, we present analysis, design and show experimental results of a new type of CMOS based power amplifier (PA) known as class-O Aref et al. (ISSCC Digest of Technical Papers, 2015). Modern CMOS based PAs design is constrained by three fundamental trade-offs, i.e. linearity, efficiency and reliability. More precisely, for a standalone PA, unless advanced and expensive solutions are employed, no such PA architecture exists which is able to meet aforementioned design trade-offs. Theoretical insight is needed to understand the origin of performance trade-offs and the possible solutions to counter them. Class-O is a novel out-of-the-box solution to meet these tough challenges. Our prototype amplifier is a highly linear low-band 706 MHz 4G long term evolution (LTE) compatible class-O RF power amplifier in 130 nm CMOS technology for handheld wireless applications. The class-O architecture uses two sub-amplifiers working together as one grand PA. These two sub-amplifiers are common-source (CS) and common-drain (CD) amplifiers working in parallel feeding a common load with high linearity without the need for digital predistortion (DPD). The prototype chip is measured and characterized with continuous wave (CW), modulated signal and reliability measurements. With CW measurements, 1-dB compression point (P$$_{1\,{\mathrm{dB}}}$$1dB) of 30.6 dBm and peak power added efficiency (PAE) of 45.2 $$\%$$% is achieved. For the modulated signal measurements, the amplifier is tested with 16-QAM 20 MHz LTE signal with peak-to-average-power ratio of 6.54 dB. The amplifier meets the stringent LTE specs with an adjacent channel power ratio (ACPR) less than ΕΊ30 dBc for both EUTRA and UTRA1 with average output power of 27 dBm and PAE above 20 $$\%$$%. Owing to the voltage following between gate source junctions in the common-drain amplifier in addition to cascode structure of common source amplifier, the stress is significantly reduced at the transistor terminals. The reliability is demonstrated by operating the amplifier in nominal and worst voltage-standing-wave-ratio (VSWR) conditions.
- Subjects :
- Engineering
Power-added efficiency
Current-feedback operational amplifier
business.industry
Amplifier
020208 electrical & electronic engineering
RF power amplifier
Electrical engineering
Differential amplifier
020206 networking & telecommunications
Common source
02 engineering and technology
Surfaces, Coatings and Films
Hardware and Architecture
Signal Processing
Hardware_INTEGRATEDCIRCUITS
0202 electrical engineering, electronic engineering, information engineering
Electronic engineering
Linear amplifier
business
Direct-coupled amplifier
Subjects
Details
- ISSN :
- 15731979 and 09251030
- Volume :
- 89
- Database :
- OpenAIRE
- Journal :
- Analog Integrated Circuits and Signal Processing
- Accession number :
- edsair.doi...........c93d9ceb62fe2b9103b9908fb6c54622
- Full Text :
- https://doi.org/10.1007/s10470-016-0815-0