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Steep Slope Tunnel FET Simulation

Authors :
Yung-Chun Wu
Yi-Ruei Jhan
Source :
3D TCAD Simulation for CMOS Nanoeletronic Devices ISBN: 9789811030659
Publication Year :
2017
Publisher :
Springer Singapore, 2017.

Abstract

The simplest way for increasing the transistor density in the wafer is to reduce the feature size of transistor.

Subjects

Subjects :
Materials science
business.industry
Transistor
Hardware_PERFORMANCEANDRELIABILITY
Condensed Matter::Mesoscopic Systems and Quantum Hall Effect
Computer Science::Other
law.invention
Computer Science::Hardware Architecture
Computer Science::Emerging Technologies
Hardware_GENERAL
Feature (computer vision)
law
Hardware_INTEGRATEDCIRCUITS
Optoelectronics
Steep slope
Wafer
business
Hardware_LOGICDESIGN

Details

ISBN :
978-981-10-3065-9
ISBNs :
9789811030659
Database :
OpenAIRE
Journal :
3D TCAD Simulation for CMOS Nanoeletronic Devices ISBN: 9789811030659
Accession number :
edsair.doi...........cd9ed97dd6fe63ed8f6b6eee97a0f1d4
Full Text :
https://doi.org/10.1007/978-981-10-3066-6_7
Full Text Access
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