Energy-delay tradeoffs in negative capacitance FinFET based CMOS circuits

Negative capacitance based transistors are being considered as competent candidates in the low power regime due to their excellent switching characteristics. In this work we use a physics based compact model for negative capacitance (NC) FinFETs to study device-circuit interactions focusing on the delay and energy dissipation aspects of NC-FinFET based CMOS circuits. Our modeling approach involves coupling of the Landau-Devonshire model of ferroelectric materials with the standard BSIM-CMG model of FinFET. State of the art 22 nm technology node n- and p-FinFETs are chosen as the internal MOSFETs. We investigate the impact of scaling the ferroelectric thickness and variation of ferroelectric properties, namely the remnant polarization and coercive electric field on the energy-delay tradeoffs in a 17-stage ring oscillator circuit.