Back to Search
Start Over
Pragmatic design of nanoscaleimulti-gate CMOS
- Source :
- IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
- Publication Year :
- 2005
- Publisher :
- IEEE, 2005.
-
Abstract
- Three-dimensional numerical device simulations are done to gain physical insights on multi-gate FinFETs, which portend the infeasibility of nanoscale triple-gate CMOS, and process/physics-based device/circuit simulations are done to check the concept of pragmatic nanoscale double-gate CMOS design, showing encouraging performance projections near the end of the SIA 2003 ITRS (2003).
- Subjects :
- Process (engineering)
business.industry
Electrical engineering
Hardware_PERFORMANCEANDRELIABILITY
Integrated circuit design
CMOS
Nanoelectronics
Hardware_INTEGRATEDCIRCUITS
Electronic engineering
Field-effect transistor
Hardware_ARITHMETICANDLOGICSTRUCTURES
business
Nanoscopic scale
Hardware_LOGICDESIGN
Subjects
Details
- Database :
- OpenAIRE
- Journal :
- IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004.
- Accession number :
- edsair.doi...........d415d8911e93cc0326205a7a5b4d39a0