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Evaluation of Low Order Stress Models for Use in Co-Design Analysis of Electronics Packaging
- Source :
- ASME 2019 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems.
- Publication Year :
- 2019
- Publisher :
- American Society of Mechanical Engineers, 2019.
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Abstract
- Co-design and co-engineering have the potential to improve the design of electronics packaging significantly. A co-designed approach moves away from the sequential approach of an electrical layout followed by a mechanical module design, and then the addition of a heat sink. Replacing it with an approach that addresses the electrical, thermal, and mechanical design simultaneously during the initial design. The goal is to evaluate the design space quickly, considering both the thermal and mechanical stress aspects together. ParaPower is a low order fast running parametric analysis tool, developed by the Army Research Laboratory (ARL), that allows rapid evaluation of package temperatures and coefficient of thermal expansion (CTE) induced stresses throughout the design space. The model uses a 3D nodal network to calculate device temperatures and thermal stresses. In order to rapidly evaluate the design space both the thermal and stress models must be reduced order and provide reasonable results on coarse grids. In the case of the stress model, the goal is a low order relationship between the temperatures and the CTE induced stresses. This paper compares three different low order models for stress. The first uses a more traditional planar module design. This assumes a substantial substrate or heat spreader as the base for the module assembly. The second model is less restrictive, eliminating the requirement for a substrate. The third model also eliminates the substrate requirement, but also allows for in-plane distribution of the stresses. The first two models do not account for the in-plane distribution. Two geometries are considered, a standard power module with a substantial substrate and a stacked novel module with no clear substrate layer. Results for both geometries and the three stress models are compared to finite element analysis (FEA) using SolidWorks, beginning with a thermal analysis followed by a stress analysis based on the temperature solution. All three models run roughly two orders of magnitude faster than the FEA and they correctly predict the trends in the CTE induced stresses.
Details
- Database :
- OpenAIRE
- Journal :
- ASME 2019 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems
- Accession number :
- edsair.doi...........d7509f047bb2208d8ed0bc4a21c7c2ca