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SOT and STT-Based 4-Bit MRAM Cell for High-Density Memory Applications
- Source :
- IEEE Transactions on Electron Devices. 68:4384-4390
- Publication Year :
- 2021
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 2021.
-
Abstract
- This article presents a multilevel design for spin–orbit torque (SOT)-assisted spin-transfer torque (STT)-based 4-bit magnetic random access memory (MRAM). Multilevel cell (MLC) design is an effective solution to increase the storage capacity of MRAM. The conventional SOT-MRAMs enable an energy-efficient, fast, and reliable write operation. However, unlike STT-MRAM, these cells take more area and require two access transistors per cell. This poses significant challenges in the use of SOT-MRAMs for high-density memory applications. To address these issues, we propose an MLC that can store 4 bits and requires only three access transistors. The effective area per bit of the proposed cell is nearly 58% lower than that of the conventional 1-bit SOT-MRAM cell. The combined effect of SOT and STT has been incorporated to design SOT-STT-based MLC that enables more energy-efficient and faster write operation than the regular MLCs. The results show that SOT–STT-based 4-bit MLC is 52.9% and 40% more efficient in terms of latency and energy consumption, respectively, when compared to 3-bit SOT-/STT-based MLC.
- Subjects :
- Magnetoresistive random-access memory
Hardware_MEMORYSTRUCTURES
Computer science
business.industry
Reliability (computer networking)
Transistor
Energy consumption
4-bit
Electronic, Optical and Magnetic Materials
law.invention
Amplitude modulation
law
Torque
Electrical and Electronic Engineering
Latency (engineering)
business
Computer hardware
Subjects
Details
- ISSN :
- 15579646 and 00189383
- Volume :
- 68
- Database :
- OpenAIRE
- Journal :
- IEEE Transactions on Electron Devices
- Accession number :
- edsair.doi...........dbcb90ba1cce4a1223751f3bd9515e36