High-Performance Dual Gate Amorphous InGaZnO Thin Film Transistor With Top Gate to Drain Offset

We report the dual gate (DG) amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor (TFT) with a top-gate (TG) drain offset (LTG(Off)) structure under dual-gate driving. The TFT shows an on/off current ratio of ~107, subthreshold swing of 0.23 V/dec, and field-effect mobility (μFE) of 14.6 cm2/Vs when LTG(Off) is 5 μm, which is 30% reduction compared to the conventional DG TFT with no drain offset (μFE=20.9 cm2/Vs). The Technology computer-aided design simulation indicates the electron concentration of ~1016 /cm3 at the offset region near top gate insulator/a-IGZO interface when LTG(Off) is 5 μm. The fabricated TFT exhibits stable performance under positive bias temperature stress with a threshold voltage shift of +0.1 V.