Modeling and Separate Extraction Technique for Gate Bias-Dependent Parasitic Resistances and Overlap Length in MOSFETs

We report a technique for separate extraction of extrinsic source/drain (S/D) resistances ( $R_{\mathrm {Se}}/R_{\mathrm {De}})$ and gate bias ( $V_{{\mathbf {GS}}})$ -dependent but channel length (L)-independent intrinsic source/drain ( $R_{\mathrm {Si}}/R_{\mathrm {Di}})$ resistances for the overlap region in MOSFETs. For extraction of the overlap length ( $L_{\mathrm {ov}})$ in the heavily doped S/D regions, an analytical capacitance model for the depletion region is employed with the gate-to-source and gate-to-drain capacitance–voltage ( $C_{{{G-S}}}$ , $C_{{{G-D}}})$ characteristics. After verifying the extracted overlap length through a 2-D technology computer-aided design simulation, we successfully extract $\mathrm{V}_{\mathrm {\mathbf {GS}}}$ -dependent $R_{\mathrm {\mathbf {Si}}}= 0.9{\sim }3.7~\Omega $ and $R_{\mathrm {\mathbf {Di}}}= 1.0{\sim }3.9~\Omega $ in an n-channel MOSFET with $W=140~\mu $ m and $L=0.35 ~\mu $ m. In addition, $V_{\mathrm {\mathbf {GS}}}$ - and $L$ -independent extrinsic S/D resistances are separately extracted to be $R_{\mathrm {Se}}=5.1~\Omega $ and $R_{\mathrm {De}}= 5.0~\Omega $ , respectively.