Statistical evaluation of critical path delay in CNFET-based circuits in the presence of CNT fabrication imperfections

The presence of metallic tubes and CNT diameter variation impacts delay of critical paths in CNFET circuits. Consequently, variations in critical path delays impact functional yield. We propose to predict circuit performance and yield using a statistical approach, rather than the worst-case method, to the critical path delay evaluation. We consider the CNT diameter variation and the number of tubes per transistor variation caused by the removal of unwanted metallic tubes. For the set of ISCAS'85 combinational benchmark circuits, we tested with initial presence of 10% and 20% metallic tubes, that are all being removed, we are able to show a functional yield between 92.04% and 99.95%, and between 20.95% and 94.05%, respectively. We assumed delay degradation not larger than 1.3x as compared to the initial 0% of metallic tubes. The algorithm proposed to statistically evaluate path delay in the presence of variations has a time complexity of O(V log V +VE), where E is the number of gates and V is the number of nodes in the circuit. The results show the reduction of statistically calculated critical path delay as compared to the worst-case calculations. This indicates that it would be possible to manufacture a CNFET-based circuit with acceptable delay and functional yield, even in the presence of fabrication imperfections. To predict the behavior of these circuits and to design them efficiently it is necessary to use a statistical approach to the design process.