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Investigating the Performance of Hardware Transactions on a Multi-Socket Machine

Authors :
Trevor Brown
Victor Luchangco
Alex Kogan
Yossi Lev
Source :
SPAA
Publication Year :
2016
Publisher :
ACM, 2016.

Abstract

The introduction of hardware transactional memory (HTM) into commercial processors opens a door for designing and implementing scalable synchronization mechanisms. One example for such a mechanism is transactional lock elision (TLE), where lock-based critical sections are executed concurrently using hardware transactions. So far, the effectiveness of TLE and other HTM-based mechanisms has been assessed mostly on small, single-socket machines. This paper investigates the behavior of hardware transactions on a large two-socket machine. Using TLE as an example, we show that a system can scale as long as all threads run on the same socket, but a single thread running on a different socket can wreck performance. We identify the reason for this phenomenon, and present a simple adaptive technique that overcomes this problem by throttling threads as necessary to optimize system performance. Using extensive evaluation of multiple microbenchmarks and real applications, we demonstrate that our technique achieves the full performance of the system for workloads that scale across sockets, and avoids the performance degradation that cripples TLE for workloads that do not.

Details

Database :
OpenAIRE
Journal :
Proceedings of the 28th ACM Symposium on Parallelism in Algorithms and Architectures
Accession number :
edsair.doi...........e18d61311130a04d1c69fc0572d40429