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An integrated test concept for switched-capacitor dynamic MOS RAM's

Authors :
M.R. Guidry
T.C. Lo
Source :
IEEE Journal of Solid-State Circuits. 12:693-703
Publication Year :
1977
Publisher :
Institute of Electrical and Electronics Engineers (IEEE), 1977.

Abstract

An approach to dynamic MOS RAM testing has been developed. This paper deals in particular with the test problems of switched-capacitor (or single-transistor) MOS RAMs. Test procedures are developed from an understanding of the technology with which the memory circuits are built. The associated design weaknesses and failure modes are first reviewed, and four simple pattern-sensitivity programs are generated. Finally, an efficient test flow is recommended for rigorous functional verification as well as design and yield improvements.

Subjects

Subjects :
Integrated injection logic
Functional verification
Application-specific integrated circuit
Computer science
Hardware_INTEGRATEDCIRCUITS
Electronic engineering
Mixed-signal integrated circuit
Electrical and Electronic Engineering
Switched capacitor
Pin compatibility

Details

ISSN :
1558173X and 00189200
Volume :
12
Database :
OpenAIRE
Journal :
IEEE Journal of Solid-State Circuits
Accession number :
edsair.doi...........e30119c395150a079b0fd0f5d083aca1
Full Text :
https://doi.org/10.1109/jssc.1977.1050980
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