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A 2.5GHz ADPLL with PVT-insensitive ΔΣ dithered time-to-digital conversion by utilizing an ADDLL
- Source :
- ISCAS
- Publication Year :
- 2014
- Publisher :
- IEEE, 2014.
-
Abstract
- A ΔΣ all-digital delay-locked loop (ADDLL) is proposed to realize a PVT-insensitive time-to-digital converter (TDC) with enhanced linearity in an all-digital phase-locked loop (ADPLL). With the proposed TDC, poor timing resolution and nonlinearity problems are mitigated, enabling a low cost, low comparison frequency TDC design without using the advanced CMOS technology. A novel digitally-controlled delay line (DCDL) is proposed to ensure monotonous and linear mapping between a digital control word and a total time delay. A phase error compensator (PEC) is employed to calibrate periodic phase error of the proposed TDC. A 2.5GHz ADPLL is designed in 0.18μm CMOS. Simulation results show that the proposed method effectively reduces fractional spurs caused by the TDC.
Details
- Database :
- OpenAIRE
- Journal :
- 2014 IEEE International Symposium on Circuits and Systems (ISCAS)
- Accession number :
- edsair.doi...........e3f9cc8cd4272f3e47cc17466093a4e0