TSV-Free Vertical Interconnection Technology Using Au-Si Eutectic Bonding for MEMS Wafer-Level Packaging

Developments of advanced Vertical Interconnection Technologies have been indispensable parts of achieving MEMS three-dimensional (3D) integration. This paper presents a TSV-free Vertical Interconnection Technology using Au-Si eutectic bonding applied on MEMS wafer-level packaging (WLP), which simplifies processes and promotes all-Si fabrication abilities in MEMS 3D WLP. Specifically, by forming Au-Si ohmic contacts in Au-Si bonding, it is cost-efficacious to employ low-resistivity Si columns (rather than conventional metal TSV structures) in Cap wafers as vertically electrical pathways while accomplishing sealing functions. Based on testing results of signal interfacing and hermetic packaging for MEMS devices, the proposed technology possesses extensive application prospects.