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A 68-GHz Loss Compensated Distributed Amplifier Using Frequency Interleaved Technique in 65-nm CMOS Technology

Authors :
Yue-Ming Wu
Ta-Shun Chu
Yu-Hsien Kao
Source :
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 30:29-39
Publication Year :
2022
Publisher :
Institute of Electrical and Electronics Engineers (IEEE), 2022.

Abstract

This article presents a frequency interleaved technique (FIT) that can be applied to add resonant peaks in the response of distributed amplifier (DA) for loss compensation and then a frequency-interleaved distributed amplifier (FIDA) that can achieve a high-gain and wide-bandwidth frequency response by summing multiple overlapping distinct-band frequency responses through a distributed configuration. A detailed discussion was introduced to verify the FIDA and a DA was implemented using the FIT. The reported 65-nm CMOS FIDA chip occupies an area of 0.9 x 0.95 mm² and achieves a 17.2 dB small-signal power gain, 2-68 GHz -3-dB bandwidth, gain bandwidth product (GBW) of 478 GHz, and gain ripple of less than 2 dB, while consuming 120 mW under 1.2 V.

Details

ISSN :
15579999 and 10638210
Volume :
30
Database :
OpenAIRE
Journal :
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Accession number :
edsair.doi...........e806349c117c2ade449e611062975c94
Full Text :
https://doi.org/10.1109/tvlsi.2021.3124605