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Leakage-Power-Aware Scheduling With Dual-Threshold Voltage Design

Authors :
Takeshi Yoshimura
Cong Hao
Wei Zhong
Song Chen
Yu Zhu
Nan Wang
Source :
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24:3067-3079
Publication Year :
2016
Publisher :
Institute of Electrical and Electronics Engineers (IEEE), 2016.

Abstract

The exponential increase in leakage power and the substantial power-saving opportunities provided by scheduling have made dual-threshold voltage (dual- $V_{\mathrm{ th}}$ ) an attractive choice for low-leakage-power designs. In this paper, we work under the assumption that functional units (FUs) are allocated after scheduling, and fully explore the solution space of scheduling with dual- $V_{\mathrm{ th}}$ operations to optimize the leakage power of the FUs. First, a binding conflict graph (BCG)-based scheduling method is presented to minimize the number of FUs. Second, the BCG-based method is extended to allow scheduling with dual- $V_{\mathrm{ th}}$ operation targeting the minimization of leakage power. In timing-constrained scheduling, each operation in the data flow is initialized with low- $V_{\mathrm{ th}}$ . Then, starting from an operation schedule with the timing constraint satisfied, we scale the sets of low- $V_{\mathrm{ th}}$ operations in the off-critical paths with high- $V_{\mathrm{ th}}$ so as to reduce the number of low- $V_{\mathrm{ th}}$ FUs without increasing the total delay. Finally, a scheduling method for minimizing the leakage power under both timing and resource constraints is presented. The results of benchmark tests show that the proposed algorithms can reduce the leakage power reported in previous works by 10.2% while maintaining high circuit performance.

Details

ISSN :
15579999 and 10638210
Volume :
24
Database :
OpenAIRE
Journal :
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Accession number :
edsair.doi...........e865e50c85e335364358dd8baf85caeb
Full Text :
https://doi.org/10.1109/tvlsi.2016.2535221