A −20 dBm Passive UHF RFID Tag IC With MTP NVM in 0.13-μm Standard CMOS Process

A fully integrated passive ultrahigh-frequency (UHF) RF identification (RFID) tag integrated circuit (IC) based on Chinese UHF RFID standard (GJB 7377.1) is proposed. An optimized voltage multiplier with threshold compensation and leakage current suppression is designed to improve the RF-DC power conversion efficiency, which is more than 58% for different load current. A system clock constraint condition and proposed digital baseband (BB) algorithm instead of clock calibration is introduced to ensure correct demodulation of the forward link from reader to tag and back link frequency (BLF) tolerance from tag to reader. Moreover, a 2Kb multi-time programmable (MTP) non-volatile memory (NVM) in standard CMOS process without any additional masks and process modification is designed and implemented to significantly save the manufacture cost of the chip. The proposed RFID tag IC is fabricated using a $0.13-\mu \text{m}$ one-poly-five-metal (1P5M) standard CMOS process with an area of $620\times 660\,\,\mu \text{m}^{2}$ and a power consumption of 4.8 $\mu \text{W}$ and 11.5 $\mu \text{W}$ for reading and writing operations, respectively. The tag with antenna gain of 2 dBi shows successful reading detection at distances up to 17 m in the case of 4 W Equivalent Isotropically Radiated Power (EIRP) from reader.