Solution for high-performance Schottky-source/drain MOSFETs: Schottky barrier height engineering with dopant segregation technique

MLA

A. Kinoshita, et al. “Solution for High-Performance Schottky-Source/Drain MOSFETs: Schottky Barrier Height Engineering with Dopant Segregation Technique.” Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004, Jan. 2004. EBSCOhost, https://doi.org/10.1109/vlsit.2004.1345459.

APA

A. Kinoshita, Junji Koga, Atsushi Yagishita, Ken Uchida, & Yoshinori Tsuchiya. (2004). Solution for high-performance Schottky-source/drain MOSFETs: Schottky barrier height engineering with dopant segregation technique. Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. https://doi.org/10.1109/vlsit.2004.1345459

Chicago

A. Kinoshita, Junji Koga, Atsushi Yagishita, Ken Uchida, and Yoshinori Tsuchiya. 2004. “Solution for High-Performance Schottky-Source/Drain MOSFETs: Schottky Barrier Height Engineering with Dopant Segregation Technique.” Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004, January. doi:10.1109/vlsit.2004.1345459.