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A CMOS electrically reprogrammable ASIC with multi-level random logic capabilities
- Source :
- 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
- Publication Year :
- 2005
- Publisher :
- Institute of Electrical and Electronics Engineers, 2005.
-
Abstract
- A 24-pin electrically-reprogrammable ASIC, implemented in CMOS EEPROM technology with two-layer polysilicon and two-layer metal, providing user logic complexity of 600-800 gate equivalents, will be described. Speeds of 15ns per internal logic level have been obtained with 50mW consumption.
- Subjects :
- Diode–transistor logic
AND-OR-Invert
Pass transistor logic
Computer science
Depletion-load NMOS logic
law.invention
PMOS logic
Application-specific integrated circuit
law
Hardware_INTEGRATEDCIRCUITS
Electronic engineering
Pull-up resistor
Logic optimization
Digital electronics
business.industry
Logic family
Logic level
Emitter-coupled logic
Resistor–transistor logic
Programmable logic device
Programmable Array Logic
Integrated injection logic
CMOS
Logic gate
business
Random logic
Computer hardware
Hardware_LOGICDESIGN
EEPROM
Subjects
Details
- Database :
- OpenAIRE
- Journal :
- 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
- Accession number :
- edsair.doi...........eead581dcfd55e853de6c16e1ff8a9bb
- Full Text :
- https://doi.org/10.1109/isscc.1986.1156901