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System-level design language standard needed
- Source :
- IEEE Design & Test of Computers. 21:592-593
- Publication Year :
- 2004
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 2004.
-
Abstract
- The combination of SystemVerilog, SystemC, and the property specification language (PSL) promises a powerful and flexible foundation for design. Together, these standards address clear needs for emerging software-rich designs; critical capabilities for these standards include advanced verification features such as solvers and constrained random testing. This combination of standards brings powerful assertion capabilities that, with PSL, provide a bridge to formal verification and the ability to apply assertions across multiple design languages.
- Subjects :
- Electronic system-level design and verification
Functional verification
Computer science
Programming language
Specification language
SystemVerilog
Formal methods
computer.software_genre
Intelligent verification
Hardware and Architecture
Property Specification Language
Electrical and Electronic Engineering
Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION
Formal verification
computer
Software
computer.programming_language
Subjects
Details
- ISSN :
- 15581918 and 07407475
- Volume :
- 21
- Database :
- OpenAIRE
- Journal :
- IEEE Design & Test of Computers
- Accession number :
- edsair.doi...........eed890df7fa88e896c1272220afb4cd8