Design of 14-bit Digital Decimation Filter for Transimpedance Amplifier Based Sensor Application

In this paper, a design of a 14-bit digital decimation filter for transimpedance amplifier (TIA) based sensor application is presented. TIA is used for detecting very small variations in the current for highly sensitive sensor applications. The output of TIA is digitized by a high-resolution ADC. The Continuous-Time sigma-delta modulator analog-to-digital converters (CT-SDM ADC) offer a high resolution with CIC based digital filter which reduces the overall power consumption. The proposed digital filter design comprised of three integrators, a digitally controlled decimator, three comb filters, and a digital filter controller. It eliminates the use of power hungry multiplier blocks. Filter controller part controls the output data rate and effective resolution of CT-SD ADC. The proposed filter is designed in Verilog HDL and it is implemented on 0.18um CMOS technology. The digital filter output from the chip is processed by LabVIEW for performance evaluation and ENOB of 13.12 bits measured. Also, the output of TIA is digitized and measured the pluses from the photodiode.