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VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache
- Source :
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24:858-870
- Publication Year :
- 2016
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 2016.
-
Abstract
- In this paper, we investigate the feasibility of voltage adjustment in a large capacity cache, and propose the architecture of voltage-adaptable nonuniform cache access (VANUCA) that exploits near-threshold computing and multivoltage domain to approach the limit of $V_{\rm dd}$ in a low-power cache. However, the adoption of near-threshold voltage (NTV) leads to a rocketing error probability in SRAM arrays, which has to be addressed by effective fault-tolerant techniques. Instead of using error correction code or data duplication, the VANUCA exploits the natural data redundancy across the whole memory hierarchy to enable fast fault recovery in the NTV cache. Based on the discovered data resilience and the multi- $V_{\rm dd}$ architecture, the VANUCA is able to match vulnerable/invulnerable data clusters to available high-/low-voltage domains by utilizing the data migration mechanism in dynamic NUCA. The proposed VANUCA includes two important architectural techniques: 1) static assignment that assumes a fixed voltage domain partitioning and 2) DataMotion that dynamically fits the working set into heterogeneous cache banks through $V_{\rm dd}$ switching. Experimental results show that the VANUCA achieves considerable improvements in energy efficiency over the conventional single-voltage domain NUCA cache.
- Subjects :
- Cache coloring
Computer science
Working set
02 engineering and technology
Parallel computing
Cache-oblivious algorithm
Cache pollution
01 natural sciences
Cache invalidation
Write-once
0103 physical sciences
0202 electrical engineering, electronic engineering, information engineering
Redundancy (engineering)
Static random-access memory
Electrical and Electronic Engineering
Cache algorithms
010302 applied physics
Multi-core processor
Hardware_MEMORYSTRUCTURES
Memory hierarchy
MESIF protocol
020202 computer hardware & architecture
Smart Cache
Hardware and Architecture
Data redundancy
Bus sniffing
Page cache
Cache
Software
Subjects
Details
- ISSN :
- 15579999 and 10638210
- Volume :
- 24
- Database :
- OpenAIRE
- Journal :
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Accession number :
- edsair.doi...........f2f30c5ce1614ae73e334c87b23ea7a0
- Full Text :
- https://doi.org/10.1109/tvlsi.2015.2424440