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Towards IP integration on SoC: a case study of high‐throughput and low‐cost wrapper design on a novel IBUS architecture

Authors :
Jiang Lu
Xiaokun Yang
Ishaq Unwala
Shi Sha
Source :
IET Computers & Digital Techniques. 14:353-362
Publication Year :
2020
Publisher :
Institution of Engineering and Technology (IET), 2020.

Abstract

To integrate third-party intellectual properties (IPs) into a new system-on-chip (SoC) architecture is a big challenge. Therefore, this study first presents a new bus protocol named as integrated bus (IBUS), and more important, a configurable bus wrapper for connecting AXI3-interfaced IPs into IBUS is further proposed, aiming to finding the optimal balance between bus efficiency and resource cost in terms of field-programming gate array slice count, bus transfer latency, and energy consumption. As a case study, the authors implemented three IBUS wrappers for integrating three AXI3-interfaced verification IPs into an IBUS SoC. Experimental results show that their proposed work achieves a higher valid data throughput ( 1.35 × in the block test and 1.52 × in the cipher test) compared with the designs on conventional bridge-based SoC integration, as well as a large reduction in the normalised slice-time-power (18.73% in the block benchmark and 23.45% in the cipher benchmark) when setting the same weights of slice number, data transfer latency, and energy dissipation.

Details

ISSN :
1751861X and 17518601
Volume :
14
Database :
OpenAIRE
Journal :
IET Computers & Digital Techniques
Accession number :
edsair.doi...........f35d5de1b1c251fee0618644e09dffcc