Back to Search
Start Over
A 1.5µCMOS gate array with configurable ROM and RAM
- Source :
- 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
- Publication Year :
- 2005
- Publisher :
- Institute of Electrical and Electronics Engineers, 2005.
-
Abstract
- The use of 1.5μ CMOS technology to implement a 8000 equivalent gate array with double word line memory addressing on a 9.9×9.8mm2chip will be discussed. Describe, too, will be the implementation and operation of a 16b micro-processor with 1024b ROM and 256b RAM.
- Subjects :
- Diode–transistor logic
Pass transistor logic
AND-OR-Invert
Computer science
Depletion-load NMOS logic
Programmable logic array
PMOS logic
Memory address
Read-write memory
Gate array
NMOS logic
Digital electronics
Read-only memory
Hardware_MEMORYSTRUCTURES
business.industry
Sense amplifier
Logic family
Logic level
Resistor–transistor logic
Programmable logic device
Programmable Array Logic
Logic synthesis
Integrated injection logic
Computer architecture
CMOS
Logic gate
Inverter
business
Computer hardware
Subjects
Details
- Database :
- OpenAIRE
- Journal :
- 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
- Accession number :
- edsair.doi...........f4d30e136f587ff7b70c5c7ffe551605
- Full Text :
- https://doi.org/10.1109/isscc.1985.1156783