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Floating-Gate energy recovery logic
- Source :
- 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.
- Publication Year :
- 2009
- Publisher :
- IEEE, 2009.
-
Abstract
- In this paper, a new energy recovery logic based on Floating Gate transistors is presented. Floating-Gate Energy Recovery Logic (FGERL) achieves small transistor count and low voltage operation. High voltage constraint and big transistor count are major issues in adiabatic logics. Most adiabatic approaches use complex circuitry to achieve an efficient charge recovery, requiring high voltage from the power clocking circuits. Reducing transistor count reduces voltage requirement and static dissipation; less dissipating components, less power dissipated. In addition, this proposal is easy to design and implement due to its simplified architecture and single power clock scheme.
- Subjects :
- Adiabatic circuit
Engineering
Pass transistor logic
business.industry
Transistor
Logic family
Electrical engineering
Hardware_PERFORMANCEANDRELIABILITY
Condensed Matter::Mesoscopic Systems and Quantum Hall Effect
law.invention
Computer Science::Hardware Architecture
Computer Science::Emerging Technologies
CMOS
Transistor count
Hardware_GENERAL
law
Logic gate
Hardware_INTEGRATEDCIRCUITS
Electronic engineering
business
Low voltage
Hardware_LOGICDESIGN
Subjects
Details
- Database :
- OpenAIRE
- Journal :
- 2009 52nd IEEE International Midwest Symposium on Circuits and Systems
- Accession number :
- edsair.doi...........f68db41503216689d7eaebbfc976c957