A 192-pW Voltage Reference Generating Bandgap–$V_{\text{th}}$ With Process and Temperature Dependence Compensation

This article presents a methodology to design a circuit to compensate for process skew by exploiting an inherent dimension-dependent effect of process skew on change in the threshold voltage. We design a voltage reference circuit with a hybrid architecture of bandgap reference (BGR) and CMOS reference, which generates a nominal voltage level of (bandgap - threshold). By compensating the process skew of the threshold term with the proposed dimension-induced effect as well as the temperature dependence, the circuit achieves the simultaneous benefits of BGR and CMOS references. For verification, the circuit was fabricated in three wafers of a 0.18- $\mu \text{m}$ CMOS including extreme slow and fast corners. With an active area of 0.0045 mm2, it consumes 192 pW at room temperature. Measurement from 45 chips (15 chips per wafer) shows untrimmed process/voltage/temperature variations of 0.53%, 0.020%/V, and 33 ppm/°C, respectively.