Cite
Failure Analysis of 65nm CMOS Integrated Nanoscale ReRAM Devices on a 300mm Wafer Platform
MLA
Maximilian Liehr, et al. “Failure Analysis of 65nm CMOS Integrated Nanoscale ReRAM Devices on a 300mm Wafer Platform.” 2022 IEEE International Integrated Reliability Workshop (IIRW), Oct. 2022. EBSCOhost, https://doi.org/10.1109/iirw56459.2022.10032747.
APA
Maximilian Liehr, Jubin Hazra, Karsten Beckmann, & Nathaniel Cady. (2022). Failure Analysis of 65nm CMOS Integrated Nanoscale ReRAM Devices on a 300mm Wafer Platform. 2022 IEEE International Integrated Reliability Workshop (IIRW). https://doi.org/10.1109/iirw56459.2022.10032747
Chicago
Maximilian Liehr, Jubin Hazra, Karsten Beckmann, and Nathaniel Cady. 2022. “Failure Analysis of 65nm CMOS Integrated Nanoscale ReRAM Devices on a 300mm Wafer Platform.” 2022 IEEE International Integrated Reliability Workshop (IIRW), October. doi:10.1109/iirw56459.2022.10032747.