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A digital calibration technique for timing mismatch in a four-channel time-interleaved ADCs
- Source :
- 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).
- Publication Year :
- 2016
- Publisher :
- IEEE, 2016.
-
Abstract
- A digital calibration technique for timing mismatch in a four-channel time-interleaved ADCs is presented. The calibration principle is as follows. Firstly, we use delay units to have the clock of the first channel aligned with the channel that needs to be calibrated and do subtraction. Secondly, we use a digital sampling module and an error determination module to detect the timing mismatch between them. Lastly, a method of variable delay line is used to compensate the mismatch. The mismatch detection and compensation form a feedback loop that can achieve a real-time tracking and correcting. Simulation results showed that this technique can be applied to any channel TIADC and has the timing mismatch calibrated quickly and correctly by the virtue of a smaller hardware.
- Subjects :
- Computer science
020208 electrical & electronic engineering
Subtraction
02 engineering and technology
Feedback loop
Compensation (engineering)
Time–frequency analysis
Sampling (signal processing)
Line (geometry)
0202 electrical engineering, electronic engineering, information engineering
Calibration
Electronic engineering
020201 artificial intelligence & image processing
Communication channel
Subjects
Details
- Database :
- OpenAIRE
- Journal :
- 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)
- Accession number :
- edsair.doi...........fc09cb77d40989f715b599b44e3ac0d0