Shoot-through protection for an inverter consisting of the next-generation IGBTs with gate impedance reduction

Attention has been paid to the next-generation IGBT toward CMOS compatible wafer processes, which can be driven by a 5-V logic level due to its low threshold gate voltage. This low threshold voltage makes the so-called shoot-through fault severer. Even though the switching speed of the IGBT is intentionally reduced, the shoot-through fault can happen. This paper presents shoot-through protection for an inverter consisting of the next-generation IGBTs with gate impedance reduction. Theoretical analysis reveals the criterion of the gate impedance with taking parasitic parameters of the inverter into account.