SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs

MLA

Xingyu Tian, et al. SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-Based FPGAs. Jan. 2022. EBSCOhost, https://doi.org/10.48550/arxiv.2208.10770.

APA

Xingyu Tian, Zhifan Ye, Alec Lu, Licheng Guo, Yuze Chi, & Zhenman Fang. (2022). SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs. https://doi.org/10.48550/arxiv.2208.10770

Chicago

Xingyu Tian, Zhifan Ye, Alec Lu, Licheng Guo, Yuze Chi, and Zhenman Fang. 2022. “SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-Based FPGAs,” January. doi:10.48550/arxiv.2208.10770.