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Multilevel Dataflow-Driven Macro Placement Guided by RTL Structure and Analytical Methods

Authors :
Alex Vidal-Obiols
Marc Galceran-Oms
Jordi Petit
Jordi Cortadella
F. Martorell
Universitat Politècnica de Catalunya. Doctorat en Computació
Universitat Politècnica de Catalunya. Departament de Ciències de la Computació
Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
Source :
UPCommons. Portal del coneixement obert de la UPC, Universitat Politècnica de Catalunya (UPC)
Publication Year :
2021
Publisher :
Institute of Electrical and Electronics Engineers (IEEE), 2021.

Abstract

When RTL designers define the hierarchy of a system, they exploit their knowledge about the conceptual abstractions devised during the design and the functional interactions between the logical components. This valuable information is often lost during physical synthesis. This paper proposes HiDaP, a novel multi-level algorithm that uses RTL information and analytical methods for the macro placement problem of modern designs dominated by multi-cycle connection pipelines. By taking advantage of the hierarchy tree, the netlist is divided into blocks containing macros and standard cells, and their dataflow affinity is inferred considering the register latency and flow width of their interaction. The layout is represented using slicing structures and generated with a top-down algorithm capable of handling blocks with both hard and soft components. An adaptive multi-objective cost function is used to simultaneously minimize wirelength, timing, overlap and distance to preferred locations, which can be user-defined or generated by analytic methods (spectral and force-directed). These techniques have been applied to a set of large industrial circuits and compared against state-of-theart commercial and academic placers, and also to handcrafted floorplans generated by expert back-end engineers. The proposed approach outperforms previous algorithmic methods and can produce solutions with better wirelength and timing than the best handcrafted floorplans. Post-routing layouts are almost brought to timing closure and DRC cleanness with minimal engineer modification, showing that the generated floorplans provide an excellent starting point for the physical design flow and contribute to reduce turn-around time significantly. This work has been partially supported by a grant from Inphi Corporation and funds from the Spanish Ministry for Economy and Competitiveness and the European Union (FEDER funds) under grant TIN2017-86727-C2-1-R, and the Generalitat de Catalunya (2017 SGR 786).

Details

ISSN :
19374151 and 02780070
Volume :
40
Database :
OpenAIRE
Journal :
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accession number :
edsair.doi.dedup.....2d632d12d32016a8b7e1222e79ca4379