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High speed cycle approximate simulation for cache-incoherent MPSoCs

High speed cycle approximate simulation for cache-incoherent MPSoCs

Authors :
Miles Gould
Nigel Topham
Christopher Thompson
Source :
ICSAMOS
Publication Year :
2013

Abstract

We present a new high speed cycle-approximate simulator, addressing an important, neglected category of multi-core systems: deeply-embedded cache-incoherent MPSoCs. We take advantage of the unique properties of these systems to increase the parallelism of the simulation. In doing so we achieve performance not possible using previous simulation techniques, without compromising the accuracy of the results. We present quantitative performance results across a large range of simulated NoC designs, comprising 1 to 64 cores. On average we simulate at 5.9 MIPS, with simulation speeds reaching 373 MIPS in the best case. Comparing against FPGA implementations we demonstrate that the simulator manages this with an average timing error of only 2.1%.

Details

Database :
OpenAIRE
Journal :
ICSAMOS
Accession number :
edsair.doi.dedup.....2eaa4bb301630a4284c93038a8d74dc6
Full Text :
https://doi.org/10.1109/SAMOS.2013.6621110