On The Development of a Reliable Gate Stack for Future Technology Nodes Based on III-V Materials

In this work, we discuss how the insertion of a LaSiOx layer in between an in-house IL passivation layer and the high-k has moved the III-V gate stack into the target window for future technology nodes. The insertion of this LaSiOx layer in the gate stack has reduced the Dit and Nbt below the target level of 5×1011 /eV.cm2 and 3×1010 /cm2 (target at 10 years operation: ΔVfb