Back to Search Start Over

Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

Authors :
V. Fadeyev
D. Das
F. A. Di Bello
Ian Shipsey
M. Buckland
M R M Warren
Ivan Peric
D. Su
Gregor Kramberger
Daniela Bortoletto
Kirk Arndt
Jie Zhang
Mathieu Benoit
Zhijun Liang
Martin Hoeferkamp
Z. Galloway
Wen Yi Song
Luigi Vigani
L. B. A. H. Hommels
Igor Mandić
C.J. Kenney
Philippe Grenier
Abraham Seiden
I. M. Gregor
Marcel Michael Stanitzki
Rui Wang
Sally Seidel
Angelo Dragone
F. Ehrler
K. Kanisauskas
Francesco Rubbo
P. Caragiulo
Alexander Grillo
S. McMahon
C. Tamma
H. M. X. Grabas
Richard Bates
Hongbo Zhu
Andrew Blue
S. D. Worm
Lingxin Meng
J. Segal
Marko Mikuž
R. Plackett
F. F. Wilson
Q. Xiu
Richard Nickerson
Renato Turchetta
Jens Dopke
Craig Buttar
Dzmitry Maneuski
J. J. John
F. Martinez-Mckinney
J. Volk
Todd Brian Huffman
A. A. Affolder
P. Phillips
Daniel Muenstermann
Source :
Nuclear instruments & methods in physics research / A 831, 189-196 (2016). doi:10.1016/j.nima.2016.05.092
Publication Year :
2016

Abstract

Nuclear instruments & methods in physics research / A 831, 189 - 196(2016). doi:10.1016/j.nima.2016.05.092<br />ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.<br />Published by North-Holland Publ. Co., Amsterdam

Details

Language :
English
Database :
OpenAIRE
Journal :
Nuclear instruments & methods in physics research / A 831, 189-196 (2016). doi:10.1016/j.nima.2016.05.092
Accession number :
edsair.doi.dedup.....3ba2315292d2b2f838b3bf0a0245adf9
Full Text :
https://doi.org/10.1016/j.nima.2016.05.092