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Experimental and numerical results correlation during extreme use of power MOSFET designed for avalanche functional mode

Authors :
Richard Lallemand
Jean-Louis Blanchard
Jean-Michel Morelle
Gérard Coquery
Blaise Rouleau
Gael Blondel
Laurent Dupont
Laboratoire des Technologies Nouvelles (INRETS/LTN)
Institut National de Recherche sur les Transports et leur Sécurité (INRETS)
Valeo CEE
VALEO
VALEO CEE
VALEO VES R&D Département
Source :
Microelectronics Reliability, Microelectronics Reliability, Elsevier, 2010, 50 (9-11), pp 1804-1809. ⟨10.1016/j.microrel.2010.07.127⟩
Publication Year :
2010
Publisher :
Elsevier BV, 2010.

Abstract

Cost, weight and size reduction constrained designers of power electronic for micro hybrid vehicle to use power MOSFET under extreme conditions like avalanche mode. This paper shows the influence of the solder voids onto the die temperature distribution of a specifically designed power MOSFET. In the first part of this paper, a methodology is presented to perform fast dynamic temperature measurements during MOSFET avalanche (400 A–80 μs). In the second part of the paper, a comparison between experimental results and finite elements electro-thermal simulation is shown for power MOSFET operating in high conduction mode (500 A–100 ms). Finally the correlated numerical model is used to evaluate the sensitivity to solder voids of the chip temperature distribution.

Details

ISSN :
00262714
Volume :
50
Database :
OpenAIRE
Journal :
Microelectronics Reliability
Accession number :
edsair.doi.dedup.....5b39f699b4a8fd4c2dfffb2a8afa41eb
Full Text :
https://doi.org/10.1016/j.microrel.2010.07.127