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Resistive memories for spike-based neuromorphic circuits
- Source :
- 2017 IEEE International Memory Workshop (IMW), 2017 IEEE International Memory Workshop (IMW), May 2017, Monterey, United States. ⟨10.1109/IMW.2017.7939100⟩
- Publication Year :
- 2017
- Publisher :
- HAL CCSD, 2017.
-
Abstract
- Conference of 9th IEEE International Memory Workshop, IMW 2017 ; Conference Date: 14 May 2017 Through 17 May 2017; Conference Code:128262; International audience; In the last decade machine learning algorithms have proven unprecedented performance to solve many real-world detection and classification tasks, for example in image or speech recognition. Despite these advances, there are still some deficits. First, these algorithms require significant memory access thus ruling out an implementation using standard platforms (e.g. GPUs, FPGAS) for embedded applications. Second, most machine leaning algorithms need to be trained with huge data sets (supervised learning). Resistive memories (RRAM) have demonstrated to be a promising candidate to overcome both these constrains. RRAM arrays can act as a dot product accelerator, which is one of the main building blocks in neuromorphic computing systems. This approach could provide improvements in power and speed with respect to the GPU-based networks. Moreover RRAM devices are promising candidates to emulate synaptic plasticity, the capability of synapses to enhance or diminish their connectivity between neurons, which is widely believed to be the basis for learning and memory in the brain. Neural systems exhibit various types and time periods of plasticity, e.g. synaptic modifications can last anywhere from seconds to days or months. In this work we proposed an architecture that implements both Short-And Long-Term Plasticity rules (STP and LTP) using RRAM arrays. We showed the benefits of utilizing both kinds of plasticity with two different applications, visual pattern extraction and decoding of neural signals. LTP allows the neural networks to learn patterns without training data set (unsupervised learning), and STP makes the learning process very robust against environmental noise.
- Subjects :
- Computer science
Process (engineering)
02 engineering and technology
Learning algorithms
Speech recognition
Machine learning
computer.software_genre
01 natural sciences
RRAM
Unsupervised learning
Education
0103 physical sciences
Timing circuits
Neuromorphic computing
0202 electrical engineering, electronic engineering, information engineering
[INFO]Computer Science [cs]
Artificial synapses
Field-programmable gate array
010302 applied physics
Artificial neural network
Learning systems
Spiking neural networks
business.industry
Resistive memory (rram)
Synaptic modification
020208 electrical & electronic engineering
Supervised learning
Program processors
Resistive random-access memory
Neuromorphic engineering
Computer architecture
Neuromorphic circuits
Embedded application
Spike (software development)
Artificial intelligence
Short term plasticity
business
computer
Memory architecture
Neural networks
Random access storage
Subjects
Details
- Language :
- English
- Database :
- OpenAIRE
- Journal :
- 2017 IEEE International Memory Workshop (IMW), 2017 IEEE International Memory Workshop (IMW), May 2017, Monterey, United States. ⟨10.1109/IMW.2017.7939100⟩
- Accession number :
- edsair.doi.dedup.....5b456912f4b7c306bd26c13a3dacb8cc