Design of notched gate processes in high density plasmas

In less than ten years, we will be approaching the limits of the complementary metal-oxide-semiconductor technology with transistor gate length of between 10 and 30 nm. In the present article, we present a type of process allowing the design of gates having a bottom dimension smaller than the top dimension (the so-called “notched gate”). We discuss the design of the notched gate process with respect to a typical gate etch process and give some details on the sidewall passivation layer engineering. Finally, some results of critical dimension control across a 200-mm-diam wafer are shown and the potential implementation of the process in manufacturing is discussed.