Front End Readout Electronics of the MicroBooNE Experiment

MicroBooNE experiment is to build a ∼170 tons Liquid Argon (LAr) Time Projection Chamber (TPC) detector that will observe interactions of neutrinos from the on-axis Booster Neutrino Beam and off-axis NuMI Beam at Fermi National Accelerator Laboratory. The experiment will address the low energy excess observed by the MiniBooNE experiment, measure low energy neutrino cross sections, and serve as the necessary next step in a phased program towards massive Liquid Argon TPC detectors. MicroBooNE TPC will have 3 readout wire planes with 8,256 wires/signal channels. All the signals will be pre–amplified, shaped, digitized and pre-processed online before recording for offline analysis of a wide variety of physics programs. To optimize the detector performance and signal-to-noise ratio, analog front end ASIC designed in 180 nm CMOS technology will be deployed and operated in LAr. Pre-amplified and shaped detector signals will be differentially driven to ADC boards operated in detector hall where signals are digitized and prepared for online data pre-processing in FPGAs. This article is an overview of the front end readout architecture of the MicroBooNE experiment, which describes the development of the front end readout electronics and preliminary test results.