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Experimental Efficiency Evaluation of Stacked Transistor Half-Bridge Topologies in 14 nm CMOS Technology
- Source :
- Electronics, 10 (10), Electronics, Vol 10, Iss 1150, p 1150 (2021), Electronics, Volume 10, Issue 10
- Publication Year :
- 2021
- Publisher :
- MDPI, 2021.
-
Abstract
- Different Half-Bridge (HB) converter topologies for an Integrated Voltage Regulator (IVR), which serves as a microprocessor application, were evaluated. The HB circuits were implemented with Stacked Transistors (HBSTs) in a cutting-edge 14 nm CMOS technology node in order to enable the integration on the microprocessor die. Compared to a conventional realization of the HBST, it was found that the Active Neutral-Point Clamped (ANPC) HBST topology with Independent Clamp Switches (ICSs) not only ensured balanced blocking voltages across the series-connected transistors, but also featured a more robust operation and achieved higher efficiencies at high output currents. The IVR achieved a maximum efficiency of 85.3% at an output current of 300 mA and a switching frequency of 50 MHz. At the maximum measured output current of 780 mA, the efficiency was 83.1%. The active part of the IVR (power switches, gate-drivers, and level shifters) realized a high maximum current density of 24.7 A/mm2.<br />Electronics, 10 (10)<br />ISSN:2079-9292
Details
- Language :
- English
- ISSN :
- 20799292
- Database :
- OpenAIRE
- Journal :
- Electronics, 10 (10), Electronics, Vol 10, Iss 1150, p 1150 (2021), Electronics, Volume 10, Issue 10
- Accession number :
- edsair.doi.dedup.....7ad98eb8ce77a20f21e562137cfa610c