An auto-calibrated neural spike recording channel with feature extraction capabilities

Comunicación presentada al "V VLSI Circuits and Systems" celebrado en Praga (República Checa) el 18 de Abril del 2011.
This paper presents a power efficient architecture for a neural spike recording channel. The channel offers a selfcalibration operation mode and can be used both for signal tracking (to raw digitize the acquired neural waveform) and feature extraction (to build a PWL approximation of the spikes in order to reduce data bandwidth on the RF-link). The neural threshold voltage is adaptively calculated during the spike detection period using basic digital operations. The neural input signal is amplified and filtered using a LNA, reconfigurable Band-Pass Filter, followed by a fully reconfigurable 8-bit ADC. The key element is the ADC architecture. It is a binary search data converter with a SCimplementation. Due to its architecture, it can be programmed to work either as a PGA, S&H or ADC. In order to allow power saving, inactive blocks are powered off depending on the selected operation mode, ADC sampling frequency is reconfigured and bias current is dynamically adapted during the conversion. Due to the ADC low input capacitance, the power consumption of the input LNA can be decreased and the overall power consumption of the channel is low. The prototype was implemented using a CMOS 0.13um standard process, and it occupies 400um x 400um. Simulations from extracted layout show very promising results. The power consumption of the complete channel for the signal tracking operations is 2.8uW, and is increased to 3.0uW when the feature extraction operation is performed, one of the lowest reported.
This work has been supported by the Spanish Ministry of Science and Innovation under grant TEC2009-08447, the Junta de Andalucía under grant TIC-02818 and the 2007-2013 FEDER Programme.