Local lateral integration of 16-nm thick Ge nanowires on silicon on insulator substrates

In this contribution, we report on the growth of horizontal Ge nanowires inside extremely thin tunnels surrounded by oxide. This is achieved through selective lateral growth of Ge on silicon-on-insulator (001) substrates. The 16 nm high tunnels are formed by HCl vapor etching of Si followed by Ge growth in the same epitaxy chamber. First, the benefit of growing the Ge nanowires at high temperature was highlighted to homogenize the length of the nanowires and achieve a high growth rate. Afterwards, we showed that increasing the tunnel depth led to a significant reduction in the growth rate. Finally, transmission electron microscopy showed that no defects were present in the Ge nanowires. These results are encouraging for the planar co-integration of heterogeneous materials on Si.In this contribution, we report on the growth of horizontal Ge nanowires inside extremely thin tunnels surrounded by oxide. This is achieved through selective lateral growth of Ge on silicon-on-insulator (001) substrates. The 16 nm high tunnels are formed by HCl vapor etching of Si followed by Ge growth in the same epitaxy chamber. First, the benefit of growing the Ge nanowires at high temperature was highlighted to homogenize the length of the nanowires and achieve a high growth rate. Afterwards, we showed that increasing the tunnel depth led to a significant reduction in the growth rate. Finally, transmission electron microscopy showed that no defects were present in the Ge nanowires. These results are encouraging for the planar co-integration of heterogeneous materials on Si.