Motion compensation sample processing for HDTV H.264/AVC decoder

This work present a sample processing architecture to the H.264/AVC, the new video coding standard of the ITU-T and ISO/IEC, main profile motion compensation video decoder. The architecture processes luma and chroma samples in parallel, with one luma and two chroma datapaths. The sample processing is formed by the quarter sample interpolation, weighted prediction, median to bidirectional processing and clipping. The design implemented both in FPGA and VLSI are able to decode HDTV (1080x1920), 30 frames per second, at real-time at 100 and 83.9 MHz clock cycle, respectively.