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The relentless march of the MOSFET gate oxide thickness to zero
- Source :
- Scopus-Elsevier
-
Abstract
- The narrowest feature of an integrated circuit is the silicon dioxide gate dielectric (3–5 nm). The viability of future CMOS technology is contingent upon thinning the oxide further to improve drive performance, while maintaining reliability. Practical limitations due to direct tunneling through the gate oxide may preclude the use of silicon dioxide as the gate dielectric for thicknesses less than 1.3 nm, however.
- Subjects :
- Materials science
business.industry
Gate dielectric
Electrical engineering
Equivalent oxide thickness
Time-dependent gate oxide breakdown
Integrated circuit
Condensed Matter Physics
Atomic and Molecular Physics, and Optics
Surfaces, Coatings and Films
Electronic, Optical and Magnetic Materials
law.invention
CMOS
Gate oxide
law
MOSFET
Optoelectronics
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality
business
High-κ dielectric
Subjects
Details
- Database :
- OpenAIRE
- Journal :
- Scopus-Elsevier
- Accession number :
- edsair.doi.dedup.....9e8c023448ee63f79ccd788f0bb73bcb