Prospects for charge sensitive amplifiers in scaled CMOS

Due to its low cost and flexibility for custom design, monolithic CMOS technology is being increasingly employed in charge preamplifiers across a broad range of applications, including both scientific research and commercial products. The associated detectors have capacitances ranging from 50 fF to several hundred pF, and applications call for pulse shaping from tens of ns to tens of /spl mu/S, and constrain the available power per channel from tens of /spl mu/W to tens of mW. At the same time a new technology generation, with changed device parameters, appears every 2 years or so. The optimum design of the front end circuitry is examined taking into account submicron device characteristics, weak inversion operation, the reset system, and power supply scaling. Experimental results from recent prototypes will be presented. We will also discuss the evolution of preamplifier topologies and anticipated performance limits as CMOS technology scales down to the 0.1 /spl mu/m/1.0 V generation in 2006.