Performance Evaluation of CNTFET-based Digital Circuits: A Review

In this paper we review a procedure in order to carry out static and dynamic analysis of basic digital circuits. At first, for static analysis, we implement a simple DC model for CNTFETs already proposed by us, verifying the validity of the obtained results through a comparison with those of Wong model. Then, to carry out the dynamic analysis, we consider both the quantum capacitance effects and the sub-threshold current. At last we analyze the timing performances of a NOT gate in order to define the optimal working conditions, emphasizing that the proposed method can be used to analyze the timing performance of any CNTFET-based logic gate.