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The SARC architecture
- Source :
- Recercat. Dipósit de la Recerca de Catalunya, instname, UPCommons. Portal del coneixement obert de la UPC, Universitat Politècnica de Catalunya (UPC)
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Abstract
- The SARC architecture is composed of multiple processor types and a set of user-managed direct memory access (DMA) engines that let the runtime scheduler overlap data transfer and computation. The runtime system automatically allocates tasks on the heterogeneous cores and schedules the data transfers through the DMA engines. SARC's programming model supports various highly parallel applications, with matching support from specialized accelerator processors.
- Subjects :
- Multi-core processor
Computer science
Accelerator
Parallel computing
computer.software_genre
Arquitectura d'ordinadors
Set (abstract data type)
Runtime system
Parallel processing (DSP implementation)
Programming model
Hardware and Architecture
Multicore
Programming paradigm
Operating system
System on a chip
Heterogeneous computing
Heterogeneous architecture
ddc:004
Electrical and Electronic Engineering
Direct memory access
computer
Informàtica::Arquitectura de computadors [Àrees temàtiques de la UPC]
Software
Subjects
Details
- Database :
- OpenAIRE
- Journal :
- Recercat. Dipósit de la Recerca de Catalunya, instname, UPCommons. Portal del coneixement obert de la UPC, Universitat Politècnica de Catalunya (UPC)
- Accession number :
- edsair.doi.dedup.....c92d21094b6bec797ebf186e70405005