An ageing-aware digital synthesis approach

Due to the shrinkage of CMOS technology, wear-outmechanisms such as Bias Temperature Instability (BTI) haveraised growing concerns for circuit reliability. BTI can causea threshold voltage shift in CMOS devices and consequentlyincrease circuit delay. This paper presents an ageing-aware gate-leveloptimization approach that can be used in a modernsynthesis process. It aims to optimize a circuit to give improvedlifetime reliability under given area and timing constraints. A newsensitivity metric is proposed as a function of area increase, delayreduction, degradation reduction and design constraints. Thissensitivity metric can be adjusted to select the most favourablegates in terms of circuit timing, lifetime or both. By iterativelyup-sizing the gates with the highest sensitivity, our proposedoptimization flow can meet any realizable area and timingconstraints, to give up to 3.3x lifetime improvement.