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Optimization of the 65-nm CMOS Linear Front-End Circuit for the CMS Pixel Readout at the HL-LHC
- Publication Year :
- 2021
-
Abstract
- The linear front-end is the analog processor chosen for the final integration into the pixel readout chip for the high-luminosity upgrade of the CMS experiment at the large hadron collider. The front-end has been included in the RD53A chip, designed by the CERN RD53 collaboration and submitted in 2017. An optimized version of the front-end has been designed, submitted, and tested in the framework of the RD53B developments. The optimization is mainly concerned with the time-walk performance of the front-end and with its threshold tuning capabilities. The article describes in detail such design improvements together with the results from the characterization of a small prototype chip including a 16 $\times $ 16 pixel matrix featuring both the RD53A and RD53B versions of the front-end. Test results show a significant reduction, about 10 ns for input signals close to the threshold, of the time-walk in the RD53B front-end, featuring a threshold dispersion smaller than 65 electrons r.m.s. after exposure to a total ionizing dose of 1 Grad of X-rays.
- Subjects :
- Physics
Nuclear and High Energy Physics
Large Hadron Collider
Pixel
Physics::Instrumentation and Detectors
Transconductance
Detector
Chip
Settore ING-INF/01 - Elettronica
Front and back ends
ionizing radiation effects
Upgrade
CMOS front-end electronics
Nuclear Energy and Engineering
CMOS
high-luminosity large hadron collider (HL-LHC)
pixel readout chip
Electronic engineering
Electrical and Electronic Engineering
low-noise analog front-end
Subjects
Details
- Language :
- English
- Database :
- OpenAIRE
- Accession number :
- edsair.doi.dedup.....e848d89062cb9296fe1fccad3cbad926